With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption.

M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes, achieving:

• D-PHY v3.0: up to 9 Gbps per lane
• C-PHY v2.1: up to 6.5 Gsps per trio

Key technologies include:

• Adaptive receiver equalization (RxEQ)
• Multi-bandwidth architecture
• Tx/Rx equalization optimization

M31 MIPI C/D PHY IP supports stable signal integrity from intra-chip connections to over-long channels while maintaining power efficiency and performance.

Why Do AR/VR and Imaging Systems Require High-Efficiency MIPI Interfaces?

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Modern imaging systems demand both high resolution and high frame rate, significantly increasing interface bandwidth requirements.

System architectures in AR/VR and imaging applications are also more complex. Signals may travel across intra-chip, inter-chip, and over-long channels. This introduces higher insertion loss and signal integrity challenges.

Therefore, MIPI interfaces must deliver:

• Optimized power consumption under constrained conditions
• Higher data throughput
• Efficient transmission mechanisms

Bandwidth Challenges from High Resolution and High Frame Rate

• Increasing sensor resolution
  Image sensors have evolved from megapixels to tens of megapixels, increasing data volume per frame.
• Higher resolution and frame rate in AR/VR
  Requirements such as 4K/8K resolution and ≥90 Hz frame rate significantly increase data throughput.
• Improved image quality requirements
  HDR, color accuracy, and low noise require higher bit depth and additional metadata.

These factors drive the need for significantly higher interface bandwidth.

More Complex and Challenging Channel Conditions

MIPI channels now span multiple scenarios:

• Intra-chip: Short distance with low loss, but affected by parasitics and crosstalk at high speed
• Standard channel: Defined by MIPI specifications, typically PCB connections
• Inter-module: Longer PCB traces and connectors increase loss and reflections
• Over-long channel (beyond MIPI spec): Higher insertion loss and stricter bandwidth constraints

Key challenges:

• Higher insertion loss
  High-frequency attenuation increases near Nyquist frequency
• Signal integrity degradation
  Reflections, crosstalk, and jitter reduce eye opening and increase BER
• Power constraints
  Battery-powered systems require strict power efficiency

How Does M31 MIPI C/D-PHY Improve Transmission Performance?

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M31 integrates MIPI C-PHY and D-PHY into a single combo architecture, providing flexibility between efficiency and simplicity. This reduces die area and development cost while supporting diverse applications.

Dual-Standard Combo Architecture

The single PHY IP supports both:

• MIPI D-PHY v3.0
• MIPI C-PHY v2.1

Shared analog and digital resources reduce system complexity and allow flexible mode selection.

Key advantages:

• Application flexibility
  C-PHY is preferred for high bandwidth, while D-PHY suits mature or cost-sensitive designs
• Performance and cost balance
  One IP supports both standards, reducing duplication and die area

MIPI C-PHY vs D-PHY Comparison

MIPI C-PHY offers higher efficiency and throughput than D-PHY, but at the cost of greater design complexity. This is primarily due to its encoding scheme and clock recovery architecture, which require additional resources for high-speed analog design and timing recovery implementation.

	D-PHY	C-PHY
Signaling	Source Synchronous	Embedded clock
Energy efficiency	Lower	Higher
Area	Smaller	Larger
Pin count	4	3
Flexibility	All lanes synchronous	Independent trios
Packaging	Simpler	More complex
Application	Widely used	Enhancement, co-existing with D-PHY

MIPI C-PHY

Uses trio encoding and embedded clock. Improves data efficiency (coding gain). Requires complex CDR and decoding.

MIPI D-PHY

Uses separate clock and data. Simpler design but requires more pins and scalability is limited at high speed.

What Performance Can MIPI Achieve on N3P and N3C?

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Data Rate and Resolution Capability

On TSMC N3P and N3C processes, M31 MIPI PHY achieves up to 9 Gbps per lane for D-PHY and up to 60 Gbps total throughput for C-PHY, enabling support for high-resolution video from 4K@120 FPS to 8K@60 FPS.

This performance meets the bandwidth and efficiency requirements of AR/VR and advanced imaging applications.

M31 implementation details include:

D-PHY v3.0

• 9 Gbps per lane
• 4 lanes → ~36 Gbps total
• Supports 4K @ 120 FPS (30% blanking)

D-PHY provides a mature and simple architecture. With multi-lane scaling, it remains widely adopted in mobile and imaging systems.

C-PHY v2.1

• 6.5 Gsps / Trio
• 3~4 trios → ~45–60 Gbps
• Supports 8K @ 60FPS（20% Blanking）

C-PHY uses an embedded clock and encoding mechanism (coding gain) to improve data efficiency. It delivers higher throughput with equal or fewer pins, making it suitable for high-bandwidth and power-sensitive applications.

Performance, Power, and Area（PPA）

	4-Lane D-PHY @ 9Gbps	3-Trio C-PHY @ 6.5 Gsps
Tx Power	65 mW	57 mW
Rx Power	38 mW	40 mW

Power Characteristics

• Tx
  C-PHY shows lower Tx power than D-PHY due to higher coding efficiency, enabling equivalent throughput with reduced switching activity and drive current.
• Rx
  C-PHY Rx consumes more power due to more complex clock/data recovery (CDR), decoding, and multi-symbol processing. D-PHY Rx is simpler due to its source synchronous architecture, resulting in lower power.

Area Characteristics

• Tx: ~ 0.112 mm²
• Rx: ~ 0.235 mm²

Tx area is smaller and mainly consists of output drivers and buffers. Rx area is larger due to EQ, CDR, and data detection circuits. In high-speed interfaces, Rx is typically more complex than Tx and dominates area.

What Are the Key Advantages of M31 MIPI IP?

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M31 MIPI C/D-PHY IP provides:

• High-speed C/D-PHY integrated architecture
• Support for both short and over-long channels
• Adaptive receiver equalization (RxEQ)
• Multi-bandwidth power optimization
• Advanced design on N3 process technologies

These capabilities help customers address common challenges in high-resolution imaging systems, including:

• Insufficient bandwidth
• Signal attenuation in long channels
• Power limitations

As a result, systems can achieve high-quality image transmission, stable connectivity, and long operating time across AR/VR, drones, and imaging platforms.

How Is Signal Integrity Maintained in Over-Long Channels?

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Channel Conditions Beyond MIPI Specifications

Under over-long channel conditions, insertion loss can be as high as 16 dB and cause severe high-frequency attenuation and inter-symbol interference. M31’s MIPI C-PHY transmission is stable maintained at 4.5 Gsps through adaptive Rx equalization and CTLE signal compensation technologies. It significantly exceeds the design capabilities of the standard MIPI channel specification.

• Over-long channel：16 dB Insertion Loss @ Nyquist
• Standard channel：9 dB Insertion Loss
• The system can still operate at 4.5 Gsps data rate

Key Technology: Adaptive Receiver Equalization (RxEQ)

Adaptive RxEQ uses CTLE and dynamic parameter adjustment to compensate for channel loss and restore signal quality.

M31 adopts:

• Multi-pole/zero CTLE (Continuous-Time Linear Equalizer)
  Adjusts frequency response to compensate high-frequency loss and restore signal edges
• Adaptive parameter tuning
  Dynamically adjusts equalization strength based on channel conditions

Measured Effects

• +35% eye margin improvement
  Increases data sampling tolerance and system stability
• ~70 ps jitter reduction
  Improves timing accuracy and CDR reliability

Tx/Rx Equalization Co-Design

M31 adopts a co-design approach for TxEQ and RxEQ to achieve optimal balance between pre-compensation at the transmitter and post-compensation at the receiver.

• Effectively compensates for high insertion loss and bandwidth limitations
• Maintains signal integrity over long-distance transmission
• Allows dynamic adjustment of equalization parameters for different data rates

TxEQ: Enhances high-frequency components before transmission to offset channel attenuation, improving signal shape before entering the channel

RxEQ: Compensates distorted signals after transmission, restoring signal integrity for accurate data detection

How Is M31 MIPI Power Optimized Across Different Bandwidth Conditions?

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Four-Level Bandwidth Design

Through a four-level bandwidth architecture, M31 D-PHY dynamically adjusts power and circuit configuration based on data rate, enabling both efficiency and performance across a wide operating range of 0.08 to 9 Gbps.

Bandwidth Level	Data Rate	Power
Low	0.08–2.5 Gbps	18 mW
Mid-low	2.5–4.5 Gbps	24 mW
Mid-high	4.5–6.5 Gbps	33 mW
High	6.5–9 Gbps	38 mW

LP and HS Mode Switching

MIPI supports dynamic switching between LP and HS mode. This is particularly important in battery-powered AR/VR and imaging applications because it enables:

• Continuous link availability
• Reduced power consumption during idle or low activity
• High bandwidth during active transmission

How Do N3P and N3C Affect MIPI Design?

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Process Positioning

N3P and N3C are optimized for different applications:

• N3P: targets high-performance applications
• N3C: targets low-power devices such as wearables

This allows MIPI interfaces to achieve optimal performance and power balance across different product segments.

Design and Layout

In advanced nodes, MIPI PHY design must consider:

• Parasitic resistance and capacitance effects
• Impact on TxEQ and RxEQ performance
• EM/IR analysis
• Monte Carlo and PVT simulation validation

Design objectives are to ensure stable operation under process variation, and to provide built-in calibration capability.

Process Migration Design Guidelines

When transitioning from N3P to N3C, electrical characteristics, power behavior, and layout effects must be re-evaluated. Besides, circuit parameters must be adjusted to maintain target specifications (data rate and signal integrity).

M31 proposes：

• N3P to N3C Migration Strategy

During migration, transistor characteristics must be re-evaluated for high-speed analog impact, including drive strength, frequency response, and noise. Circuit parameters must be adjusted to ensure target data rate and signal integrity across process conditions.

• Performance and Power Trade-off

N3P and N3C have different optimization targets. Parameters such as equalization strength, bias conditions, and operating modes must be tuned based on performance or power requirements to achieve an optimal balance.

• Layout Optimization Guidelines

In advanced nodes, parasitics significantly impact high-speed signals. Critical paths must ensure routing symmetry, impedance control, and minimized parasitics. Power and ground design must also reduce noise and IR drop to maintain system stability.

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