M31 offers a comprehensive portfolio of ultra-low-power memory IP on the 6nm process node, including ULL, eLL, and Low-VDD memory solutions. These technologies are designed to optimize power, performance, and area (PPA) for SoCs targeting Edge AI and AIoT applications that require extended standby operation and energy-efficient computing.

Typical use cases include smart wearables, environmental sensors, smart cameras, and edge AI inference devices that support applications such as image recognition and voice wake-up. These systems rely heavily on low leakage power and fast wake-up capability to maximize battery life and overall system efficiency.

Key technology advantages include:

• Reduced leakage power, with eLL memory delivering 5% to 10% lower leakage than ULL and approximately 50% lower leakage in retention mode.
• Low-voltage operation support down to 0.6V, reducing dynamic power consumption to approximately 0.64× compared to nominal voltage operation.
• Multiple power management modes that can provide up to 25x power savings, depending on the operating condition.

M31’s ultra-low-power memory IP has completed initial silicon validation and is ready to support production-ready SoC development.

Why Do Edge AI and AIoT Applications Need Ultra-Low-Power Memory IP?

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Most Edge AI and AIoT devices are battery-powered and spend the majority of their operating life in standby, monitoring, or retention modes. As a result, power consumption has become a critical design consideration. Unlike traditional computing platforms that primarily focus on maximizing performance, AIoT systems place greater emphasis on energy efficiency, battery life, and fast wake-up capability.

What Are the Power Characteristics of AIoT Applications?

Edge AI and AIoT devices exhibit power consumption profiles that are fundamentally different from those of traditional high-performance computing systems. Their operation is typically characterized by the following attributes:

1. Extended Standby Periods
   Devices spend most of their time in a low-activity state. For example, sensors and wearable devices continuously monitor their environment while performing little or no active computation.
2. Event-Driven Processing
   Computing resources are activated only when specific events occur, such as voice wake-up, image recognition, or anomaly detection.
3. Battery-Powered Operation
   Most AIoT applications rely on battery power, making energy efficiency a key requirement for maximizing operating life.
4. Always-On Functionality
   Certain memory blocks must remain powered at all times to retain data or maintain essential system functions.

To support these operating conditions, memory must not only minimize standby power consumption but also provide fast wake-up capability to enable responsive, real-time processing when the system becomes active.

Why Is Memory Leakage a Power Bottleneck?

In AIoT and low-power SoCs, memory leakage is often a major contributor to total power consumption. This is driven by both the operating characteristics of AIoT systems and the inherent nature of memory arrays.

1. Standby Time Significantly Exceeds Active Processing Time
   AIoT devices spend most of their operating life in standby or retention mode. During these periods, switching activity is minimal, meaning static power consumption, primarily caused by leakage, becomes the dominant source of power dissipation.
2. SRAM Is One of the Largest Blocks in a SoC
   Memory macros such as SRAM typically occupy a significant portion of the die area in modern SoCs. Because leakage power scales with transistor count and silicon area, memory can have a disproportionate impact on overall chip leakage.
3. Retention Mode Still Requires Data Preservation
   In retention mode, memory cannot be completely powered down because data must be preserved. A minimum supply voltage must be maintained to retain stored information, resulting in continuous leakage power.
4. Measured Results Demonstrate the Impact of Leakage Optimization
   Silicon measurement results show that eLL memory achieves approximately 50% lower leakage in retention mode compared with ULL memory. This demonstrates that leakage optimization can directly and substantially reduce standby power consumption.

Taken together, these factors explain why memory leakage becomes a critical power challenge in AIoT systems, where devices spend most of their operating life in low-activity states. Reducing leakage is therefore essential for improving energy efficiency and extending battery life.

What Ultra-Low-Power Memory IP Solutions Does M31 Offer on the 6nm Process Node?

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M31 provides a comprehensive portfolio of ultra-low-power memory compilers on the 6nm process node, including ULL (Ultra Low Leakage), eLL (Extreme Low Leakage), and Low-VDD memory solutions. Each technology is optimized for a different aspect of low-power SoC design, enabling customers to select the most suitable memory architecture based on their application requirements.

The ULL memory compiler delivers high-density, low-leakage SRAM and Register File solutions that achieve an optimal balance between power consumption and performance, making it a mainstream choice for low-power SoC designs.

The eLL memory compiler further reduces leakage by 5% to 10% compared with ULL and achieves approximately 50% lower leakage in retention mode, making it particularly well suited for long standby operation and battery-powered applications.

The Low-VDD memory compiler supports operation down to approximately 0.6V. By enabling ultra-low-voltage operation, it reduces dynamic power consumption to approximately 0.64x compared with operation at 0.75V, making it an effective solution for energy-efficient computing.

Technology	Primary Optimization Target	Applications
ULL	Balanced power and performance	General low-power SoCs
eLL	Ultra-low leakage	Long standby applications
Low-VDD	Low-voltage operation	Ultra-low-power computing

Metric	Leakage	Retention Leakage	Dynamic Power	Performance
ULL	Low	Baseline	Moderate	Balanced
eLL	Lower (5% to 10% reduction)	~ 50% of ULL	Moderately low	Optimized for low power
Low-VDD	Voltage-dependent	Design-dependent	Lowest due to low-voltage operation	Depends on operating voltage

ULL (Ultra Low Leakage) Memory Delivers High-Density, Low-Leakage SRAM and Register File Solutions

ULL is one of M31’s core low-power memory solutions on the 6nm process node. It is designed for SoCs that require an optimal balance of power, performance, and area (PPA). The ULL memory compiler provides a comprehensive portfolio of SRAM and Register File solutions optimized for low leakage and high density.

Key features of the ULL memory compiler include:

• High-density memory architectures that are well suited for area-constrained SoC designs
• Optimized leakage power while maintaining robust performance
• Support for key low-power and testability features, including redundancy, power gating, scan test, and built-in self-test (BIST)
• A versatile memory architecture suitable for mainstream low-power applications

In practical deployments, ULL memory is ideal for SoCs that require extended operating life while maintaining consistent performance, such as AIoT controllers, edge processors, and other low-power embedded systems.

eLL (Extreme Low Leakage) Memory Further Reduces Leakage by 5% to 10% and Optimizes Long-Standby Applications

eLL是在 ULL Building on the ULL architecture, eLL is designed to further minimize leakage power for applications that are highly sensitive to standby power consumption. According to M31’s characterization results, eLL achieves an additional 5% to 10% leakage reduction compared with ULL memory.

Key features and benefits of eLL memory include:

• A leakage-optimized bitcell architecture that reduces static power consumption
• Approximately 50% lower leakage in retention mode compared with ULL memory
• Ideal for applications that spend extended periods in standby mode
• Helps extend battery life in power-constrained devices

Rather than targeting maximum performance, eLL is specifically optimized to minimize leakage power. This makes it an effective solution for long-standby systems where reducing idle power consumption is a primary design objective.

Low-VDD Memory Supports Operation Down to 0.6V for Reduced Dynamic and Static Power

Low-VDD is M31’s low-voltage memory solution designed to reduce power consumption while maintaining energy-efficient operation. By supporting supply voltages as low as 0.6V, it enables significant power savings for applications where minimizing energy consumption is a key design objective.

Key features of the Low-VDD memory compiler include:

• Support for operating voltages down to 0.6V, helping reduce overall power consumption
• Significant dynamic power reduction through voltage scaling, in accordance with the dynamic power relationship
• 0.64x power consumption at 0.6V compared with operation at 0.75V
• Support for low-voltage operation in always-on blocks while simplifying overall power architecture

Low-VDD memory is particularly well suited for applications that operate at lower frequencies and can take advantage of reduced supply voltages, as well as systems with stringent energy-efficiency requirements. Typical use cases include lightweight edge inference workloads, sensor-processing systems, and always-on monitoring applications.

How Does M31 Memory IP Enable Ultra-Low-Power Operation?

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M31 achieves ultra-low-power operation through a combination of architectural and power-management techniques. Its Dual Rail architecture separates the power supplies for the memory array and peripheral circuitry, allowing each block to operate at its optimal voltage for greater power efficiency.

In addition, Dynamic Voltage and Frequency Scaling (DVFS) enables the memory to dynamically adjust voltage and frequency according to workload requirements, balancing power consumption and performance across different operating modes.

M31 memory IP also supports multiple voltage domains, allowing different functional blocks to operate at their most efficient voltage levels. This provides finer-grained power control and improves overall system energy efficiency.

Dual Rail Architecture Supports Separate VDDA and VDDP Power Domains

M31 memory IP employs a Dual Rail architecture that independently powers the memory array and peripheral circuitry to improve power optimization flexibility and efficiency. The architecture consists of two primary power domains:

• VDDA：Supplies the memory array where data is stored.
• VDDP：Supplies peripheral circuitry such as decoders, control logic, and I/O circuits.

This split power architecture allows designers to optimize the operating voltage of each block independently. For example, the peripheral circuitry can operate at a lower voltage to reduce power consumption while maintaining a sufficient voltage level in the memory array to ensure data integrity and retention.

The Dual Rail architecture also enables a wider operating voltage range, allowing the memory to adapt to different application requirements and power-performance targets.

DVFS Supports Multiple Operating Modes to Balance Power and Performance

M31 memory compiler IP supports Dynamic Voltage and Frequency Scaling (DVFS), allowing the memory to transition between different operating modes based on system requirements and workload conditions. This enables an optimal balance between power consumption and performance.

The supported operating modes include:

• High Performance
• Active
• Low Active
• Standby
• Power Shutdown

DVFS dynamically adjusts supply voltage and operating frequency according to workload demand. When higher performance is required, the memory operates at a higher voltage and frequency. During light workloads or standby conditions, both voltage and frequency can be reduced to minimize power consumption.

The design also supports multiple voltage domains, enabling different functional blocks to operate at voltage levels optimized for their specific workloads and performance requirements.

This approach is particularly well suited for AIoT applications, where workloads are often intermittent rather than continuously active. As a result, memory resources do not need to remain in high-power operating states when peak performance is not required.

How Does M31 Balance Low Power and High Performance Through Memory Architecture and Circuit Design?

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M31 combines advanced circuit techniques and configurable memory architectures to optimize power, performance, and area (PPA) on the 6nm node. Through mixed-Vt design and assist circuitry, memory can operate reliably at lower supply voltages without sacrificing stability. Wide-voltage operation further enables a single memory IP to support applications ranging from ultra-low-power standby to high-performance computing.

In addition, architectural parameters such as Bank, Mux, RPB, and Level Shifter configurations can be tuned to achieve the optimal balance among power consumption, performance, and silicon area.

Mixed-Vt and Assist Circuitry Improve Low-Voltage Stability

Reducing supply voltage is one of the most effective ways to lower power consumption. However, operating at lower voltages also increases the risk of read/write failures and circuit instability. To address these challenges, M31 employs mixed-Vt design techniques and assist circuitry to enhance memory robustness under low-voltage conditions.

Key design features include:

• Combining Low Threshold Voltage (LVT) and Standard Threshold Voltage (SVT) devices within the same circuit to balance performance and leakage
• Using assist circuitry to optimize read and write operations, improving SRAM reliability at low voltages
• Optimizing signal paths to ensure accurate data transfer even under reduced supply voltages

These techniques help maintain correct memory operation without significantly increasing power consumption, making them particularly effective for Low-VDD operation and power-saving modes.

Wide-Voltage Operation Supports Diverse Application Requirements

M31 memory compiler IP supports a wide operating voltage range, allowing a single memory design to function efficiently across multiple use cases and performance targets.

Key capabilities include:

• Operating voltage support from approximately 0.5V to 0.9V
• Compatibility with DVFS for dynamic voltage scaling based on workload conditions
• Reliable functionality at low voltages and enhanced performance at higher voltages

This wide-voltage capability enables the same memory IP to support:

• Low-power standby operation
• General-purpose computing workloads
• High-performance processing requirements

By supporting multiple operating conditions within a single IP, designers can reduce system complexity while improving integration efficiency and design flexibility.

How Do Silicon Results Validate the Power and Performance Advantages of M31 Memory IP?

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Measurement results demonstrate that eLL memory delivers approximately 9% lower power in standby mode and 51% lower power in retention mode compared with ULL memory, significantly improving energy efficiency in long-standby applications.

Under low-voltage operating conditions, M31 memory compilers can achieve up to 91% power reduction, highlighting the effectiveness of low-voltage design techniques for energy-sensitive applications.

In addition, M31 memory compilers deliver performance improvements ranging from approximately 30% to 66% under different operating conditions, demonstrating that low-power optimization can be achieved without sacrificing performance.

eLL Reduces Power Consumption by Approximately 9% in Standby Mode and 51% in Retention Mode Compared with ULL

Measured silicon data shows a significant reduction in leakage power when comparing eLL and ULL memory across low-power operating modes.

Key results include:

• 9% lower power consumption in standby mode
• 51% lower power consumption in retention mode

These results indicate that eLL memory is particularly well suited for battery-powered and long-standby applications, where minimizing static power consumption is critical to maximizing system operating life.

Power Consumption Can Be Reduced by Up to 91% Under Low-Voltage Operation

In addition to leakage optimization, M31 memory compilers deliver significant power savings through low-voltage operation. By reducing the supply voltage, both dynamic and static power consumption can be substantially lowered.

Key findings include:

• Power consumption decreases significantly as the operating voltage is reduced.
• Under low-voltage conditions, total power consumption can be reduced by up to 91%.

This reduction is primarily driven by the strong dependency of power consumption on supply voltage, making low-voltage operation an effective approach for improving energy efficiency.

This capability is particularly valuable for applications that must operate continuously while maintaining strict power budgets, such as edge sensing devices and always-on monitoring systems.

Performance Improvements of Approximately 30% to 66% Under Different Operating Conditions

While low power consumption is critical, memory performance remains equally important for modern SoCs. Measurement results show that M31 memory compilers can also deliver significant performance gains across different voltage and operating conditions.

Key results include:

• 30% performance improvement under certain operating conditions
• Performance gains ranging from 40% to 66% under other conditions

These improvements are enabled by a combination of voltage optimization, circuit-level enhancements, and memory architecture tuning. As a result, the memory maintains efficient access performance across a wide range of operating modes.

The results demonstrate that low-power optimization does not necessarily require a trade-off in performance. With the right architecture and circuit techniques, both energy efficiency and performance can be improved simultaneously.

Is M31 Memory IP Ready for Production SoC Deployment?

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M31’s ULL memory IP has successfully completed key silicon validation milestones, demonstrating that the design has been tested in actual silicon and meets the fundamental requirements for production deployment.

In addition, M31’s other memory IP offerings have reached a production-ready level, providing the functionality, design maturity, and process compatibility required for deployment in low-power SoC products.

ULL Memory Has Successfully Completed Silicon Validation

M31 M31’s ULL memory IP on the 6nm process has successfully completed initial silicon validation. The primary objective of this validation phase is to verify correlation between silicon results and design models, while confirming that the memory meets its intended functional and electrical specifications.

The validation covered several key areas:

• Successful read and write operation of the memory
• Compliance with specified operating conditions
• Stable functionality in silicon
• Validation of memory architectures including HDSP and HDOP

Completion of silicon validation demonstrates that the memory IP has progressed beyond simulation and design verification and has been successfully tested in physical silicon. This significantly reduces integration risk and allows SoC developers to rely on proven hardware behavior, minimizing the need for additional validation cycles and design iterations.

M31 Memory IP Meets the Requirements of Production-Ready SoC Designs

In addition to completing silicon validation, M31 memory IP is production-ready for SoC integration, offering the functionality, design maturity, and process compatibility required for volume production.

Key features of M31 memory IP include:

• A comprehensive memory portfolio covering both SRAM and Register File solutions
• Support for critical design-for-test and low-power features, including Redundancy, Power Gating, Scan, and BIST
• Configurable architectures that can be tailored to specific application requirements
• Proven compatibility with the target process platform, enabling smooth production deployment

Furthermore, the 6nm process node provides a mature design environment and a small modeling gap between design models and silicon behavior, improving both design predictability and the likelihood of first-silicon success.

Overall, M31 memory IP not only delivers ultra-low-power performance but also provides the level of maturity and reliability required for real-world product development and production deployment.

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