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The Optimal Solutions of TSMC 28ESF3 Platform- M31’s High Performance and High Density SRAM Compilers

Overview

High Performance SRAM and High Density SRAM are two IPs on tsmc 28nm Embedded Flash process which redefine the competitive SRAM compiler options with the variety of the advanced power modes including Nap, Retention, and Power Shutdown. Aggressively, M31 provides the source bias function to enhance the power-saving during retention mode. It provides the dual flexible solutions for outer or inter voltage bias operations for different low power applications in SoC design.
High Density SRAM contains HD 6T-bitcell for high density purpose; while High Performance SRAM contains HC 6T-bitcell for high performance requirement. All these two compilers take M31 2nd generation of low power SRAM architecture with Source Bias Enable (SBE) which supplies the alternative option during the retention mode for 70% leakage-saving, comparing to that of 28HPC+ SRAM. Furthermore, the new feature provides the Asynchronous Write-Through (AWT) function for fast data retrieval and access with flexible margin optimization for the trade-off between performance and memory capacity. The new next-generation memory design adopts the high-sigma design methodology to optimize the variety of memory capacity demands.
M31 completes the development of memory compilers on tsmc 28ESF3, which is widely used in high-speed data processing, graphics computing, power management, and handheld mobile communication design. The ULL SRAM bit cells provide the outperformance leakage and these compilers contain two devices, VT options, “SVT”&”SVT+uHVT”, to provide the attractive performance for speed and power requirements. It provides chip design more competitive characteristic for the embedded flash products.

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