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M31 PCIe 3.1 PHY IP

Overview

M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low-power architecture for the high-bandwidth applications. The PCIe 3.1 IP supports a complete range of PCIe 3.1 Base applications and is compliant with the PIPE 4.3 specification. The IP integrates high-speed mixed signal circuits to support PCIe 3.1 traffic at 8Gbps. It is backward compatible with PCIe 2.1 data rate at 5.0Gbps and PCIe 1.1 data rate at 2.5Gbps. With the supports for both TX and RX equalization techniques, the PCIe 3.1 IP can meet the requirements for different channel conditions.

Highlights

Fully compliant with PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications

  • Compliant with PIPE4.3 (PCIe) specification
  • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.3 spec
  • Supports L1 PM Substates with CLKREQ#
  • Supports L1 Clock Power Management (CPM) with CLKREQ#
  • Supports Separate Refclk Independent SSC (SRIS) architecture
  • Accessible register controls allows user specific optimization of critical Parameters (e.g. TXPLL bandwidth, TX de-emphasis level, CDR bandwidth and EQ strength)
  • Supports robust BIST functions for mass production tests
  • Available in 7nm,¬†12nm,¬†16nm, 22nm, 28nm, and 40nm process

L0_Rx_8GTps_CBB3_JitTol for PCI Express 3.0 Add-In Card

Gen3 TX Eye Diagram

Block Diagram

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