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M31 PCIe 2.1 PHY IP

Overview

M31 PCIe 2.1 transceiver IP provides a complete range of PCIe 2.1 Base applications. It is compliant with the PIPE 3.0 specification. This IP integrates high-speed mixed signal circuits to support PCIe 2.1 traffic at 5Gbps and is backward compatible with PCIe 1.1 data rate at 2.5Gbps. It is optimized for minimal die area and low power consumption. With the supports for both TX and RX equalization techniques, the PCIe 2.1 IP can meet the requirements for different channel conditions.

Highlights

Enhanced version of power/area reduced by 50%

  • Fully compliant with PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
  • Compliant with PIPE 3.0 (PCIe) specification
  • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE 3.0 spec
  • Supports L1 PM Substates with CLKREQ#
  • Supports L1 Clock Power Management (CPM) with CLKREQ#
  • Supports Separate Refclk Independent SSC (SRIS) architecture
  • Accessible register controls allows user specific optimization of critical parameters (e.g. TXPLL bandwidth, TX de-emphasis level, CDR bandwidth and EQ strength)
  • Integrated high-performance PLL to provide a variety of stand-alone clock outputs for PCIE related applications
  • Supports robust BIST functions for mass production tests
  • Available in 12nm, 14nm, 16nm, 22nm, 28nm, 40nm, and 55nm process

L0_Rx_5GTps_JitTol for PCI Express 2.0 Add-In Card

PCIe 2.1 PHY Eye Diagram

Block Diagram

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