M31 MIPI IP for Mobile/Automotive Applications – M31 MIPI M-PHY v3.1 IP
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin counts along with excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides silicon-proven and low-power M-PHY in different process nodes. The M-PHY IP follows MIPI M-PHY v3.1 spec and supports full range of high-speed (HS) and low-speed (LS) data transfer. It is compliant to the RMMI interface which allows seamless integration with upside controllers. The M-PHY IP is optimized for UFS (Universal Flash Storage) and DigRF applications. It supports not only a very short sync length for HS transmission but also a reference-less mode during LS operation. Meanwhile, M31 also provides various lane configurations for the M-PHY IP to meet different requirements of bandwidth.
- Supports RMMI interface for applications like UNIPRO protocol (UFS,CSI-3, DSI-2), and DigRF
- High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B, with scalable power consumption
- Burst mode CDR with short sync length (<16SI)
- Low speed PWM Gears from G1 to G4 with ultra-low power consumption
- Supports reference-less function during low-speed operation
- Common lane configuration facilitates the lane scalability
- Low latencies to switch to/from different power states
- Supports multiple signal amplitudes
- Supports strong BIST functions to ease the mass production tests
- Certified with ASIL-B of ISO 26262 (16nm)
- Available in 12nm, 16nm, 28nm, 40nm, and 55nm process
- MIPI M-PHY 4.0 in 7nm is coming soon.
Eye Diagram of M-PHY TX HS-G3 through Ref. Channel 2 with 6dB De-Emphasis
SJ Sens at 5824MBit