The Smallest Area and Lowest Power Standard Cell – M31 6.5 Track High Density and Low Power Standard Cell Library (HDSC) on 28/22nm
M31 proposes the competitive “6.5-track ultra-High Density Standard Cell (HDSC) for 22nm/28nm technology node”. The key features include ultra-high density layout structure, multi-channel length/multi-VT supporting, rich set of driving strengths for timing closure, and fully customized layout for minimum area consideration. The target applications are in IoT, low-power and high-integration user-specific design applications in consumer product, portable device and other high density markets. To achieve the smallest cell area, M31 utilizes the specific high density cell layout architecture and unique device placement for a variety type of cell groups. In addition, this IP type also provides rich set of combo cells. The comprehensive Low Power Solution also provides “Low Power Optimization Kit” (LPKT) and “Power Management Kit” (PMK) to reduce dynamic power and static power. Compared with the conventional 7-track standard cell library in the industry, M31’s 6.5-track cell library is able to reduce 8~13% area and 13% power use for different applications in 28nm tech-node (in the same operation frequency and operation voltage benchmarked by CPU case). Aggressively, it could reduce 8~13% area and 26.05% power in 22nm tech-node. This IP is able to assist customers in providing a more competitive product not only in “performance”, but also in terms of “power saving” and “cost efficiency”.
- Provide different type cell with the same function for area, power, and performance optimization
- Fully customized layout for minimum area consideration
- Support low power design with Low Power Optimization Kit (LPKT) and Power Management Kit (PMK) library
- Multi-channel length/Multi-VT support for low-power application
- Provide ECO library for flexibility
- Freely swap VT for speed/power optimization
- Available in 22nm and 28nm process nodes
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