USB 2.0 PHY IP
M31 provides customers a next generation USB 2.0 IP which delivers an extremely smaller die area and lower active and suspend power consumption. M31 uses a “whole new design architecture” to implement the USB 2.0 IP without sacrificing USB 2.0 related performances. The USB 2.0 IP is not only suitable for USB peripherals but also an optimized solution for SOC which is eager for “multiple USB ports”.
- Worldwide smallest USB 2.0 PHY IP (IP size of 55nm, 40nm, 28nm, and 16/12nm are smaller than 0.2mm² )
- Fully compliant with Universal Serial Bus (USB) 2.0 electrical specifications
- Compliant with UTMI+ specification (High-Speed, Full-Speed and Low-Speed functions)
- Supports clock inputs from 10/12/25/30MHz crystal oscillator or external 10/12/25/30MHz clock source
- Integrated PLL to provide a variety of stand-alone clock outputs for USB related applications
- Available in 7nm, 12nm, 14nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, and 90nm process