M31 SerDes PHY IP


M31 SerDes PHY IP provides high-performance, multi-lane capability and low-power architecture for the high-bandwidth applications. The SerDes IP has supported data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-Kr, CEI, XAUI, USXGMII, QSGMII and SGMII. With the supports for both TX and RX equalization techniques, the SerRDes IP can meet the requirements for different channel conditions.


  • Support 1.25G to 10.3125Gbps data rates and compact die area (<0.55mm² for 2-lane)
  • Support >20dB channel loss
  • Support RX loss-of-signal detect
  • Support X1, X2, and X4 lanes
  • Accessible register controls allows user specific optimization of critical parameters (e.g. TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Support both FOM for Link-EQ Training
  • Support robust BIST functions for mass production tests
  • Support Wire-Bond and Flip-Chip packages
  • Available in 7nm, 12nm, 14nm, 16nm, and 28nm process nodes

Block Diagram of SerDes in 12nm/16nm Process

TX Eye Diagram @ 10.3125Gbps

RX Jitter Tolerance @ 10.3125Gbps