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M31 PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection




Overview


M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP supports a complete range of PCIe 5.0 Base applications and is compliant with the PIPE 5.2 specification. The IP integrates high-speed mixed-signal circuits to support PCIe 5.0 traffic at 32Gbps. It is backward compatible with PCIe4.0 data rate at16 Gbps, PCIe 3.1 data rate at 8.0Gbps, PCIe 2.1 data rate at 5.0Gbps, and PCIe 1.1 data rate at 2.5Gbps. With the supports for both TX and RX equalization techniques, the PCIe 5.0 IP can meet the requirements for different channel conditions.