M31 PCIe 4.0 PHY IP for Storage and High-Bandwidth Connection – The highest speed PCIe 4.0 PHY IP with 16GT/s


M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The PCIe 4.0 IP supports a complete range of PCIe 4.0 Base applications and is compliant with the PIPE 4.4.1 specification. The IP integrates high-speed mixed signal circuits to support PCIe 4.0 traffic at 16Gbps. It is backward compatible with PCIe 3.1 data rate at 8.0Gbps, PCIe 2.1 data rate at 5.0Gbps and PCIe 1.1 data rate at 2.5Gbps. With the supports for both TX and RX equalization techniques, the PCIe 4.0 IP can meet the requirements for different channel conditions.


  • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
  • Compliant with PIPE4.4.1 (PCIe) specification
  • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 spec
  • Supports L1 PM Substates with CLKREQ#
  • Supports L1 Clock Power Management (CPM) with CLKREQ#
  • Supports Separate Refclk Independent SSC (SRIS) architecture
  • Accessible register controls allows user specific optimization of critical parameters (e.g. TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Supports both FOM and DIR mode for Link-EQ Training
  • Supports robust BIST functions for mass production tests
  • Built-in LDO for analog core power generation providing easier IC integration and lower BOM cost for SSD applications
  • Available in 7nm, 12nm, and 16nm process
  • PCIe 5.0 in 7nm process is coming soon

Block Diagram

PCIe G4 Add-in Card Far-End Eye Test

PCIe G4 Add-in Card Rx Jitter Tolerance