M31 MIPI IP for Mobile/Automotive Applications – M31 MIPI D-PHY v1.1/v1.2 IP


The D-PHY is a popular MIPI physical layer developed for mobile applications because it is a flexible, high-speed, low-power and low-cost solution. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides silicon-proven D-PHY in different process nodes. The D-PHY IP follows MIPI D-PHY v1.1/v1.2 spec and supports full range of high-speed (HS) and low-power (LP) data transfer. It is compliant to the PPI interface which allows seamless integration with upside controllers for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. Car manufacturers are also adopting MIPI specifications because the solutions are mature, relatively simple to use. M31 provides certified and compact PHY to support automotive applications.


  • Compliant with MIPI D-PHY spec up to v1.2 (by different process nodes)
  • Support MIPI DSI and CSI-2 protocol
  • Support HS data rate from 80Mbps up to 2.5Gbps per lane
  • Support LS data rate of 10Mbps and ultra-low-power mode
  • Support 1 clock lane & up to 4 data lanes
  • Support extra RX mode with 2 sets of 1 clock lane and up to 2 data lanes
  • Provide swap function for clock and data lanes to ease PCB design
  • Provide sub-LVDS compatibility (by different process nodes)
  • Provide a stand-alone parallel BIST module for mass production test
  • Certified with ASIL-B of ISO 26262 (16nm)
  • Available in 12nm, 16nm, 28nm, 40nm, and 55nm process

Block Diagram:MIPI D-PHY TX

Block Diagram:MIPI D-PHY RX