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M31 MIPI IP for Mobile/Automotive Applications – M31 MIPI D-PHY v1.1/v1.2 IP




Overview


The D-PHY is a popular MIPI physical layer developed for mobile applications with the advantages of being flexible, high-speed, low-power, and low-cost. By following the MIPI D-PHY v1.1/v1.2 specification, M31 D-PHY supports full range of high-speed (HS) and low-power (LP) data transfers. With its compliant PPI (PHY-Protocol interface), it allows seamless integrations with controllers of Camera Serial Interface (CSI-2) and Display Serial Interface (DSI). Car manufacturers are also adopting MIPI specifications because the solutions are mature, relatively simple to use. M31 provides certified and compact PHY to support automotive applications.




Highlights


  • Compliant with MIPI D-PHY spec up to v1.2 (in different process nodes)
  • Support both MIPI DSI and CSI-2 protocols
  • Support HS data rate from 80Mbps up to 2.5Gbps (per lane)
  • Support LS data rate of 10Mbps and Ultra-low power mode
  • Support 1 clock lane and up to 4 data lanes
  • Support additional RX mode with 2 sets of (1 clock lane and up to 2 data lanes)
  • Provide clock and data lane swap function to ease PCB design
  • Provide sub-LVDS compatible interface (in different process nodes)
  • Provide a stand-alone parallel BIST module for mass production tests
  • Available in 5nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm




Block Diagram:MIPI D-PHY TX





Block Diagram:MIPI D-PHY RX