M31 MIPI IP for Mobile/Automotive Applications – M31 MIPI C-PHY/D-PHY Combo v1.2 IP


The MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve throughput over bandwidth limited channel, the C-PHY is developed and is delivering 2.28 bits per symbol over three-wire trio. As a MIPI Alliance contributor and leading Interface IP provider, M31 offers silicon-proven, low-power and low-cost C-PHY/D-PHY Combo in various process nodes. Users are able to configure this Combo PHY into either D-PHY or C-PHY mode to support different applications. It is also compliant with the PPI interface, which allows seamless integration with either CIS-2 or DSI controller.


  • Compliant with MIPI D-PHY v1.2 and C-PHY v1.2 specs
  • Support both MIPI DSI and CSI-2 protocols
  • Support HS data rate from 80Mbps (0.8Gsps) up to 2.5Gbps ( 3.5Gsps ) per lane (per trio)
  • Support LS data rate of 10Mbps and Ultra-low power mode
  • Support D-PHY mode with 1 clock lane & up to 4 data lanes
  • Support C-PHY mode up to 3 trios for TX and 4 trios for RX
  • Support TX-EQ function to compensate loss of a long channel
  • Support additional D-PHY RX mode with 2 sets of (1 clock lane and up to 2 data lanes)
  • Support additional C-PHY RX mode with 2 sets of 2 trios
  • Provide D-PHY clock and data lane swap function
  • Provide C-PHY trios swap function
  • Provide a stand-alone at-speed multi-lanes (trios) parallel BIST module for mass production tests
  • Available in 5nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm

2.5Gsps C-PHY TX Eye Diagram

Block Diagram:MIPI C/D-PHY Combo TX

Block Diagram:MIPI C/D-PHY Combo RX